On the Efficiency of Reductions in p-SIMD Media Extensions

Many important multimedia applications contain a signifcant fraction of reduction operations. Although, in general, multimedia applications are characterized for having high amounts of Data Level Parallelism, reductions and accumulations are dificult to parallelize and show a poor tolerance to increases in the latency of the instructions. This is specially signifcantfor p-SIMD extensions such as MMX or AltiVec. To overcome the problem of reductions in p-SIMD ISAs, designers tend to include more and more complex instructions able to deal with the most common forms of reductions in multimedia. As long as the number ofprocessor pipeline stages grows, the number of cycles needed to execute these niultimedia instructions increases with every processor generation, severelr compromising performance. This paper presents an in-depth discussion of how reductions/accumulations are pelformed in current p-SIMD architectures and evaluates the performance trade-offs for a nearfuture highly aggressive superscalarprocessors with three different styles of p-SIMD extensions. We compare a MMX-like alternative to a MDMX-like extension that has Packed accumulators to attack the reduction problem, and we also compare it to MOM, a matrix register ISA. We will show that while packed accumulators present several advantages, they introduce artipcial recurrences that severely degrade pe rfortnance for processors with high number of registers and long latency operations. On the other hand, this paper demonstrates that longer SIMD media extensions such as MOM can take great advantage of accumulators by exploiting the associative parallelism implicit in reductions.